ULX3S Schematic Reference

This page describes selected ULX3S circuits and their connections to Hazard3-Doom. Use the schematic for the installed board revision when checking component values and FPGA package pins. See Sources de conception et lectures complémentaires for schematic sources and Contraintes de broches, schémas et révisions PCB for pin assignments.

Pushbuttons and reset 

The board provides user buttons and a power-control button. PWRBtn and BTN_PWRn identify the power-button circuit; BTN_PWRn is an active-low signal.

The FPGA can use a button as a reset input only when the pin is assigned in fpga_ulx3s.lpf and connected to reset logic in fpga_ulx3s.v. A SoC reset restarts the processor and the logic connected to that reset. It does not reload the FPGA bitstream or switch off board power.

Relevant source files:

third_party/Hazard3/example_soc/synth/fpga_ulx3s.lpf
third_party/Hazard3/example_soc/fpga/fpga_ulx3s.v
third_party/Hazard3/example_soc/soc/example_soc.v

GPIO expansion headers 

J1 and J2 expose FPGA I/O signals labeled GP and GN. A header pin number, schematic net name, FPGA package pin, and RTL signal name are separate identifiers.

The Hazard3-Doom monitor UART uses these J1 connections:

J1 monitor UART
UART	J1	USB-UART adapter
Transmit (`TxD`)	Pin 6, `GP0`	RX
Receive (`RxD`)	Pin 8, `GP1`	TX
Ground	GND	GND

For other GPIO signals, fpga_ulx3s.lpf assigns FPGA pins and fpga_ulx3s.v connects the pads to the SoC. GPIO_IN_WIDTH in example_soc.v specifies an internal input-bus width. It does not specify the number of pins on J1 or J2.

See Interfaces USB, JTAG, UART, GPIO et ESP32 for connector details.

LEDs and switches 

The board has eight user LEDs and input switches. The LPF assigns the FPGA pins; the top-level RTL defines their functions. The LED output width and GPIO input width are independent.

Clock and FPGA configuration 

The ULX3S oscillator provides a 25 MHz reference clock. The FPGA derives other clocks for the SoC, memory, and video interfaces. Clock settings are defined in the FPGA build, not by changing the oscillator.

The ECP5 can be configured through JTAG or from SPI flash. SoC reset does not replace FPGA configuration. See FPGA, horloges et domaines d’E/S and Configuration FPGA, flash et chemins de démarrage.

SDR SDRAM 

External SDR SDRAM provides application and data memory. The memory interface has a 16-bit data bus, address and bank signals, and SDRAM control signals. The memory controller performs initialization and refresh.

Hazard3-Doom connects the SoC to the SDRAM controller through ahb_sdram.v. The monitor initializes SDRAM before loading an application into it. See Mémoire externe : SDR SDRAM.

USB, UART, and JTAG 

The on-board USB interface provides FPGA programming and debug access. The board also has a six-pin JTAG header for an external adapter.

The Hazard3-Doom monitor UART uses J1 GP0 and GP1, as listed above. The monitor UART is not the USB programming connection. See Interfaces USB, JTAG, UART, GPIO et ESP32.

micro-SD and ESP32 

The micro-SD socket can hold DOOM.IMG and DOOM.WAD for loading by the monitor. These files are separate from the FPGA configuration stored in SPI flash.

The FPGA and ESP32 share SD interface signals. When the FPGA accesses the card, ESP32 GPIO14, GPIO15, GPIO2, and GPIO13 must be configured as high-impedance inputs to avoid bus contention. See Vidéo, micro-SD et stockage d’exécution and Démarrage à froid depuis micro-SD.

GPDI video 

The GPDI connector carries HDMI-compatible video signals driven by the FPGA. Hazard3-Doom converts framebuffer pixels into the output video stream in FPGA logic.

The web interface’s Screen Snip feature transfers framebuffer data over UART; it does not capture the GPDI output. See Vidéo, micro-SD et stockage d’exécution and Pipeline vidéo.

Other peripherals 

The schematic also includes audio, display, and board-support circuits. Availability to software depends on the FPGA build and its peripheral logic. Consult the LPF and top-level RTL for implemented connections.